SecureCore Project
Princeton University
Naval Postgraduate School
Information Sciences Institute
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2008 Posters
Mon, 06/18/2012 - 10:12 — szefer
SecureCore
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Year 2 Accomplishments
SecureCore
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Efficient Randomness Generation Techniques for Embedded Systems
SecureCore
Dynamic Integrity Trees for Deployable Memory Authentication
SecureCore
A Secure yet High Performance Cache Architecture
SecureCore
Memory Integrity for Secure Computing Platforms
SecureCore
SP Processor Architecture Reference Manual
SecureCore
TEC-Tree: A Low Cost and Parallelizable Tree for Efficient Defense against Memory Replay Attacks
SecureCore
Secure Key Management Architecture Against Sensor-node Fabrication Attacks
SecureCore
1 attachment
Re-examining Probabilistic Versus Deterministic Key Management
SecureCore
1 attachment
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